1. Field of the Invention
The present invention relates to a device for mounting a semiconductor package, and particularly to an improved device for mounting a semiconductor which is capable of mounting a bottom leaded semiconductor package (BLP) for testing, and to methods of fabricating the device.
2. Background of the Related Art
FIGS. 1A and 1B are, respectively, a vertical cross-sectional view and a bottom view of a BLP. As shown therein, a lead frame 2 includes a plurality of substrate connection leads 2a, the bottom portions of which are intended to be connected to a substrate (not shown). A plurality of chip connection leads 2b extend from the substrate connection leads 2a. A semiconductor chip 1 is bonded to the upper portion of the substrate connection lead 2a by an adhesive 3. A plurality of wires 4 are provided for electrically connecting chip pads (not shown) and the chip connection leads 2b of the lead frame 2. A body 5 is formed by encapsulating the wires 4, the semiconductor chip 1, and the leads 2a and 2b of the lead frame 2 using a molding resin 5. As shown on FIG. 1B, predetermined portions of the substrate connection leads 2a are partially exposed to the outside. The above art is described in U.S. Pat. No. 5,428,248, which issued Jun. 27, 1995.
The above-described bottom leaded semiconductor package is generally only used after first being subjected to an electrical characteristic test. To test the package, a solder paste is coated on the pads of a printed circuit board (PCB) 10, and the semiconductor package 20 (as shown in FIGS. 1A and 1B) is mounted thereon. Next, an infrared reflow process is performed to attach the semiconductor package 20 to the PCB 10. Such an assembly is shown in FIGS. 2A and 2B. Thereafter, the PCB 10, on which the semiconductor package 20 is mounted, is mounted on a test apparatus (not shown), and an electrical characteristic test is performed to determine whether the package has any defects. When a defect is found, the IR reflow process is performed again so as to remove the defective package, another semiconductor package is mounted in its place, and the entire PCB 10 is re-tested.
However, since the electrical characteristic test is performed only after attaching the semiconductor package 20 on the PCB 10, solder may be undesirably pasted to the semiconductor package 20. Also, because the IR reflow process is performed prior to testing, the semiconductor package 20 may incur thermal damage, thus causing defective packages.
The above references are incorporated by reference herein where appropriate for teachings of additional or alternative details, features and/or technical background.